1. Field of the Invention
The present invention is related to a capacitor of Dynamic Random Access Memory (DRAM) and a method of fabricating the same, and more particularly to a deep trench capacitor and a method of fabricating the same.
2. Description of the Related Art
As the semiconductor technology has advanced to the Deep Sub-Micron technology, the sizes of devices keep shrinking. As to the traditional structure of DRAM, the areas of capacitors have been reduced. In another aspect, software programs become large gradually, so the capacities of memories should also increase. Under the circumstance that sizes of memories should shrink and the capacities of memories should increase, the traditional method of fabricating capacitors of DRAM should be improved to satisfy the above demand.
The DRAM capacitor generally include stack capacitor and deep trench capacitor. Regardless of the type of capacitor, size reduction requirement of semiconductor devices and the technology of fabricating the small size capacitors is very complex.
FIGS. 1A-1F are a schematic cross-sectional process flow showing a prior art method of fabricating a deep trench capacitor.
Referring to FIG. 1A, first a substrate 100 is provided, and a mask layer 102 is formed over the substrate 100. Then, an etching process is performed for forming a deep trench 104 within the substrate 100. Then, a doped region 106 is formed within the substrate 100 at the bottom of the deep trench 104, which serves as an electrode of the deep trench capacitor. Next, a capacitor dielectric layer 108 is formed over the surface of the bottom of the deep trench 104. A first polysilicon layer 110 is formed within the deep trench 104 covering the capacitor dielectric layer 108, wherein the first polysilicon layer 110 serves as another electrode of the deep trench capacitor. A collar oxide layer 112 is then formed on the sidewalls of the deep trench 104 that are not covered by the first polysilicon layer 110.
Referring to FIG. 1B, a second polysilicon layer 114 is formed on the hard mask layer 102 covering the first polysilicon layer 110 and the collar oxide 112. A chemical mechanical polish process and an etching process are performed for removing a portion of the second polysilicon layer 114 and the remaining portion of the second polysilicon layer 114a is left in the deep trench 104 as shown in FIG. 1C.
Then, referring to FIG. 1D, a portion of the collar oxide layer 112 that is not covered by the second polysilicon layer 114a is removed and the remaining portion of the collar oxide layer 112a is left behind, wherein the substrate 100 at the sidewalls of the top of the deep trench is exposed.
Please referring to FIG. 1F, a third polysilicon layer 116 is formed on the mask layer 102, covering the second polysilicon layer 114a and the collar oxide layer 112a. A chemical mechanical polish process and an etching process are performed for removing a portion of the third polysilicon layer 116, and the remaining portion of the polysilicon layer 116a is left in the deep trench 104. As shown in FIG. 1F, the remaining portion of the third polysilicon layer 116a contacts the substrate 100 at the sidewalls of the top of the deep trench. Next, an active device (not shown) such as a transistor is formed on the substrate 100, and the electrode 110 of the deep trench capacitor can electrically connect to the transistor through the second polysilicon layer 114a and the third polysilicon layer 116a. 
However, in prior art, in order to form the collar oxide layer 112a on the sidewalls of the deep trench 104 as shown in FIG. 1D and to expose the substrate 100 at the sidewalls of the top of the deep trench 104, the second polysilcon layer having different removal rate compared to the collar oxide 112 should be formed first, then a portion of the collar oxide is removed for exposing the substrate 100 at the sidewalls of the top of the deep trench. Because the second polysilicon layer 114a electrically connects with the first polysilicon layer 110 and the portion of the third polysilicon layer 116a is formed on the second polysilicon layer 114a, the deep trench capacitor electrically connects to an active device through the third polysilicon layer 116a and the second polysilicon layer 114a. 
However, because the second polysilicon layer and the third polysilicon layer are formed in different process steps, dopant concentrations of the second polysilicon layer and the third polysilicon layer are therefore little different. Therefore, the difference will affect the threshold voltage of the devices.
Another issue is that resistance exists at the interface of the second polysilicon layer and the third polysilicon layer, and therefore the electrical component electrically connecting the deep trench capacitor and the active device will have a higher resistance.